Chair, Professional Activities Committees for Engineers (PACE) @ IEEE Long Island Section
Senior Design Engineer (Contract) @ IBM Microelectronics
Masters, Electrical Engineering - Microelectronics @
Mississippi State University
Over 12+ years of results-driven technical experience in physical design (PD), physical verification (PV), methodology and physical library development using industry standard electronic design automation (EDA) tools. Consistently successful in back-end design skills, such as implementing, integrating, and verifying both block and top level designs. Highly proficient in all stages of a chip design cycle with multiple
Over 12+ years of results-driven technical experience in physical design (PD), physical verification (PV), methodology and physical library development using industry standard electronic design automation (EDA) tools. Consistently successful in back-end design skills, such as implementing, integrating, and verifying both block and top level designs. Highly proficient in all stages of a chip design cycle with multiple tape out experience with industry-leading foundries such as IBM, Fujitsu and TSMC. Furthermore, uniquely qualified in front-end design skills, such as functional verification and static timing analysis (STA).
Considerable management responsibilities and interpersonal skills in teams as well as an independent individual contributor. Has led successful initiation, progress towards, and completion of initiatives as a project manager, design manager, in interfacing with clients, vendors, and host companies. Volunteers in, and has been recognized for significant contributions to, the leading professional society in the field of electrical engineering, IEEE.
Senior Physical Design Engineer @ Provide physical design implementation (Floorplanning, Power Planning, Placement & Optimization, Clock Tree Synthesis, Routing, ECO steps, Timing/SI) on projects based on sub micron technologies. From 2012 to Present (3 years) Chair, Professional Activities Committees for Engineers (PACE) @ Elected for two years term. PACE within Long Island section is a grassroots network of IEEE volunteers. The objective of PACE is to promote professional interests of IEEE's LI members. From 2011 to 2012 (1 year) Senior Design Engineer (Contract) @ Physical design, timing closures and physical verification of High Speed Serial (HSS) Links, PLL controller core and RLMs for PCIe in Cu32 IBM technology. From 2011 to 2011 (less than a year) Physical Design Consultant @ Implemented physical design, timing closure and physical verification on blocks for AMD/ATI Graphics Processor Units (GPUs) based on 28nm technology. From 2010 to 2010 (less than a year) IEEE-USA Liaison @ Coordinated with IEEE USA Headquarter in Washington DC on issues faced by local section. From 2009 to 2010 (1 year) Senior Engineer @ Provided back-end support for chip development on 90 and 65 nm technologies. Physical design for ARM9 processor and Sandbridge’s DSP included early die size estimation, floorplanning, place and route, RC extraction, timing closure, ECO, noise analysis and static & dynamic IR drop analysis.
Performed functional verification on blocks and chip level. Tasks included logic equivalency checking between RTL and synthesized netlist and netlist to netlist with extended checks on low power design: other checks covered - clock domain crossing and design constraints.
Devised automation scripts to enable repeatable P&R process on current and future chip development. Established and maintained physical design databases, evaluated and installed EDA tools being the point of contact with company engineers. From 2004 to 2009 (5 years) Member of Technical Staff (contract) @ Member of Manhattan Routing team worked with physical design team of ATI Technologies on physical implementation of memory controllers of the 90nm high performance game console.
Provided detailed feedback to the RTL team for crucial improvements to the micro-architecture to meet P&R timing closure. From 2003 to 2004 (1 year) Senior Physical Design Engineer @ Successfully completed P&R cycle for multi-million gate chips (0.18um, 0.11um). Performed floorplanning, power grid design, clock tree design, place and route, repeater insertion, physical timing closure, signal integrity closure, physical verification and tape-out.
Provided Pre-Sales technical support, interfaced with R & D on P&R methodology development and developed physical design application note. From 2001 to 2002 (1 year) Staff Engineer @ Performed physical design implementation at chip level. Taped out several high-speed, multi-million gate designs.
Interfaced with IBM's Tool & Methodology organization with issues encountered during physical design to minimize the impact in future chip development. From 1999 to 2001 (2 years) Design Engineer @ Composed and compiled code to generate schematics for multiport compilable register and memory arrays. From 1999 to 1999 (less than a year) Design Engineer @ Developed special macros requested by the customers. Performed LVS, DRC and LPE of physical layout for special macros. From 1997 to 1998 (1 year) Senior Associate Engineer (contract) @ Developed Gate Array, Standard Cell, I/O circuit libraries for RadHard and low power applications.
Performed VLSI Functional Simulation/Verification and Characterization: timing analysis and power consumption using ASX/SPICE simulation tools. From 1996 to 1997 (1 year)
Ph.D. (ABD), Electrical Engineering - VLSI Design @ Mississippi State UniversityMasters, Electrical Engineering - Microelectronics @ Mississippi State UniversityB.S., Electrical Engineering @ The University of Memphis Ahmad Haque is skilled in: Physical Design, EDA, FPGA, LEC, Floorplanning, Physical Verification, Project Management, Signal Integrity, Static Timing Analysis, TCL, VHDL, Perl, Methodology, ASIC, SoC
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