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Aditya D.

Design Verification Engineer @ Broadcom

Aditya D. Contact Details

Location:
San Francisco Bay Area
Work:
Design Verification Engineer @ Broadcom
Engineer III (Consultant) @ Qualcomm
Design Verification Engineer @ Smartplay International Inc.
Education:
Post graduate diploma, VLSI design @ UTL
About:

More than 10 years of experience in Pre Silicon Verification. My experience includes SOC verification, IP verification, VIP development, TB development. I have full cycle verification experience ie., Test planning, TB development, Functional coverage, Assertions, Testcase development, Verification execution to meet coverage and correctness goals, Gate-level simulations, and in addition ATE pattern generation and HW validation of 

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